library ieee;
use ieee.std_logic_1164.all;

entity mux2 is
    generic(n: integer);
    port(
    d0, d1: in std_logic_vector(n downto 0);
    s: in std_logic;
    y: out std_logic_vector(n downto 0)
    );
end mux2;

architecture behav of mux2 is
begin
    with s select
        y <= d0 when '0',
            d1 when '1',
            (others => '-') when others;
end behav;
